Architecture

Perpendicular lines create a shared array current.

Voltage DACs drive the bit-lines while each source-line current passes through a transimpedance amplifier and ADC. The sensing resistance connects the analog array to the available conversion range.

Trace the signal path Continue to the optimum

Crossbar operation

The design variable sits between the array and ADC.

Bit-lines (BLs) run perpendicular to source-lines (SLs), with a 1T1R bitcell at each crossing. DACs drive the BLs, and the TIA on each SL holds the line at V_DC. Activating M word-lines computes an M × N matrix-vector multiplication in one step.

Signal path. R_s, the TIA input impedance, scales the SL current reaching the ADC.
Noise path. DAC mismatch, bitcell variation, ADC clipping, and ADC quantization.
Design target. The R_s that maximizes compute SNR for the chosen device and N.

Voltage-driven resistive crossbar with perpendicular input columns, source-line current sensing, transimpedance amplifiers, and ADCs. — **Crossbar architecture.** Perpendicular bit-lines and source-lines feed one TIA and ADC per output source line. Adapted from Fig. 1(a) of the ISCAS 2022 paper.

Weight encoding

Complementary columns remove the zero-input current.

Finite R_on and R_off leave a current even at a zero dot product. Differential encoding removes it: adjacent columns receive opposite-sign inputs, and a bitcell pair stores one ternary weight. An N-term dot product therefore occupies 2N physical columns.

b_{2 k} = \begin{cases} 1, & if G_{2 k - 1} > G_{2 k} \\ 0, & if G_{2 k - 1} = G_{2 k} \\ - 1, & if G_{2 k - 1} < G_{2 k} \end{cases}

Ternary weight stored in a bitcell pair. Eq. (1) of the paper.

Signal model

Only a fraction of the ideal current reaches the readout.

R_s appears in parallel with the array resistance R_arr, so the SL delivers only a fraction S_I of the ideal current. Since R_arr ∝ 1/N, a longer dot product shrinks the signal, and lowering R_s recovers it. However, an R_s below about 500 Ω carries significant area overhead.

I_{sig} = \frac{R_{arr}}{R_{arr} + R_{s}} \sum_{k = 1}^{N} V_{2 k} Δ G_{2 k} = S_{I} I_{ideal}

Signal current on the SL. Eq. (2) of the paper.

R_{arr} = \frac{1}{\sum_{j = 1}^{2 N} G_{j}}, S_{I} = \frac{R_{arr}}{R_{arr} + R_{s}}

Array resistance and current scaling factor. Eq. (3) of the paper.

Noise model

Four non-idealities corrupt the source-line current.

I_{SL} = I_{sig} + I_{nb} + I_{nd} + I_{nc} + I_{nq}

SL current with its four noise terms. Eq. (4) of the paper.

1I_nb · Array

Bitcell variation

G_on and G_off vary across the array, modeled with a 4% standard-deviation-to-mean ratio.

2I_nd · Drivers

Input-DAC mismatch

DAC finger mismatch adds noise that grows with the input, modeled at 4% per finger.

3I_nc · ADC

Clipping

SL current beyond ±I_clip = ±2 µA saturates at the ADC rail.

4I_nq · ADC

Quantization

A B_ADC-bit ADC adds uniform noise over one step of the clipping range.

Source-line current versus ideal dot product for a ReRAM crossbar, showing clipping at plus and minus two microamperes and an inset of noisy samples scattered around the ideal line. — **Noise on the SL current.** ReRAM, N = 512, R_s = 316 Ω, 6 b ADC. Adapted from Fig. 1(b) of the ISCAS 2022 paper.

Compute SNR

Noise pushes ADC outputs off the ideal line.

Currents beyond ±I_clip collapse onto the rails, and the remaining noise scatters samples around the ideal line. Compute SNR compares the signal power with the total power of the four noise terms.

SNR = \frac{E [I_{sig}^{2}]}{E [I_{nb}^{2}] + E [I_{nd}^{2}] + E [I_{nc}^{2}] + E [I_{nq}^{2}]}

Compute SNR at the SL. Eq. (5) of the paper.

Model boundary

The limits hold under stated assumptions.

The reported limits are conditional on these assumptions and the evaluation parameters.

Binary devices. Each device takes only the states R_on and R_off.
Sensing. R_s equals the TIA input impedance.
Circuit check. The behavioral models were validated against 22 nm SPICE simulation.
Parasitics. The paper's equation omits wire parasitics. The Architect adds them with a full network model.