Behavioral model → SEC/OCCS co-design

Start with the error, then design the correction.

A behavioral model reveals how each activated row is attenuated. That spatial pattern becomes the SEC factorization, the fixed-point datapath, and the sensing architecture implemented in silicon.

QuestionWhy can two row patterns with the same ideal dot product produce different analog outputs?

MechanismBL/SL voltage gradients make contribution depend on physical row and column position.

Design responseLearn shared row factors $\gamma_i$ , normalize each column with $\theta_j$ , and stabilize sensing with OCCS.

01 · Behavioral model

Model the complete signal path.

The model couples device variation and interconnect to readout and quantization. It exposes how array size, row ordering, precision, and compensation reshape the distribution seen at the ADC output.

MRAM device	Parallel/antiparallel conductance states and MTJ variability.
Array network	Bitline and sourceline resistance, position-dependent voltage loss, and row activation.
Column formation	Differential signed weights and four binary-weighted physical columns per ADC column.
Readout	Sensor noise, column gain/offset, and 6-bit ADC quantization.
Cross-check	Ideal, nonideal, and circuit-simulation CSV comparisons across controlled sweeps.

The key observation is spatial.

The same logical activation produces a different analog contribution depending on its physical row. Near- and far-end patterns can bend to opposite sides of the ideal transfer line, with large relative error near a zero-valued dot product.

Model output: a row- and column-indexed attenuation map, raw current/ADC distributions, and matched ideal/nonideal vectors that can drive SEC architecture studies.

JxCDC 2024

Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures develops the parallel-bar behavioral/SNDR framework and validates it against the measured 22 nm MRAM prototype. JSSC 2025 carries the resulting structured attenuation into an SEC architecture built around $\alpha$ , $\gamma$ , and $\theta$ .

N=64,\quad B_{\mathrm{ADC}}=6,\quad V_{\mathrm{ref}}=20\,\mathrm{mV};\qquad \mathrm{SNDR}_{\mathrm{model}}=5.17\,\mathrm{dB},\quad \mathrm{SNDR}_{\mathrm{silicon}}=5.15\,\mathrm{dB}

Ideal arithmetic

y_{\mathrm{o}j}=\sum_{i=1}^{N}w_{ij}x_i

Every logical product contributes with unit gain.

Physical array

y_j^{(\alpha)}=\sum_{i=1}^{N}\alpha_{ij}w_{ij}x_i

$\alpha_{ij}$ captures the location-dependent analog attenuation.

SEC target

y_j^{\mathrm{SEC}}=\theta_j\sum_{i=1}^{N}\alpha_{ij}w_{ij}(\gamma_i x_i)\approx y_{\mathrm{o}j}

Learning makes $\theta_j\gamma_i\alpha_{ij}\approx1$ over the training distribution.

02 · Error abstraction

Turn parasitics into factors the architecture can act on.

Let $\alpha_{ij}$ describe the attenuation for row $i$ as observed by column $j$ . SEC applies one learned $\gamma_i$ to row $i$ across the bank, then normalizes each output column with $\theta_j$ .

y_j^{\mathrm{SEC}}=\sum_{i=1}^{N}\theta_j\gamma_i\alpha_{ij}w_{ij}x_i

$\alpha_{ij}$ captures how row position $i$ and column $j$ shape a cell’s analog contribution through BL/SL parasitics.

One $\gamma_i$ per row

Sharing the input-side correction across ADC columns avoids storing a full correction matrix.

LEARN

Fit the physical die

On-chip stochastic-gradient updates adapt $\gamma_i$ to instance-specific parasitics that are unknown before fabrication.

NORMALIZE

One $\theta_j$ per column

Output normalization absorbs column gain so that $\theta_j\gamma_i\alpha_{ij}\approx1$ statistically.

Uncompensated path

x_i

→

\alpha_{ij}

→

\mathrm{ADC}_j

Row position directly modulates the contribution delivered to each ADC column.

SEC-enabled path

\gamma_i x_i

→

\alpha_{ij}

→

\theta_j

→

y_j^{\mathrm{SEC}}

Input pre-scaling and output normalization flatten the systematic spatial response.

03 · Precision selection

Use convergence studies to freeze the fixed-point path.

Floating-point SEC establishes the algorithmic target. Quantized sweeps then choose widths that preserve convergence while bounding area and switching energy. The implemented inference scale is 7 bit, backed by a 14-bit update accumulator. A power-of-two learning rate enables shift-based updates.

Fixed-point statistical error compensation training and inference datapath — **SEC datapath.** Training updates correction state. Inference reuses the learned row scale in the input path.

Inference factor	7-bit $\gamma_i$ path selected from behavioral quantization sweeps.
Update state	14-bit accumulator retains the smaller training increments.
Learning rate	Power-of-two $\mu$ permits a shift in place of a general multiplier.
Validation	Fixed- and floating-point learning trajectories remain closely aligned.
Learning target	Hardware correction state $\gamma$ is calibrated while application-model weights remain fixed.

Comparison of floating-point and fixed-point SEC convergence — **Precision check.** Behavioral convergence is the gate between the compensation concept and the hardware widths.

04 · Circuit co-design

Coordinate array correction with offset-compensated sensing.

SEC addresses structured array error, but static mismatch and PVT sensitivity in the column sensor can still consume the available signal margin. The offset-compensated current sensor (OCCS) therefore changes both the level-shifting element and the operating sequence.

AUTO-ZERO

Capture static offset

An auto-zero phase stores mismatch before the array current is evaluated.

RESISTIVE SHIFT

Reduce PVT dependence

A resistor replaces the prior transistor level shifter to stabilize the sensing bias.

EVALUATE

Resolve a small current step

The evaluation phase presents an offset-reduced signal to the 6-bit SAR conversion path.

Circuit simulation

Monte Carlo analysis quantifies the bitline-voltage variation and reports roughly 17% OCCS area overhead relative to the prior CGFBS sensing loop.

\frac{\sigma(V_{\mathrm{BL}})}{\mathbb{E}[V_{\mathrm{BL}}]}=3.8\%\text{–}8.4\%

05 · Integrated macro

Preserve the signal definition across memory, conversion, and correction.

Each ADC column combines four binary-weighted physical columns. Differential MRAM storage and wordline selection implement signed $1\text{-bit input}\times4\text{-bit weight}$ operations. Multibit activations are evaluated bit-serially.

Full MRAM IMC macro with memory array, OCCS, SAR ADC, SEC, and control blocks — **Macro signal chain.** $512\times512$ physical cells feed 128 ADC columns, each with sensing, 6-bit conversion, SEC-related data handling, and local sequencing.

Implemented48.7%Core area occupied by ADC columns.

Implemented7.9%Core area occupied by the MRAM array.

Implemented12.2%SEC area overhead on the die.

Projection3.7%Possible SEC overhead with register storage replaced by SRAM.

Architecture resultBehavioral modeling determines the compensation structure and precision. OCCS preserves the analog margin that SEC then uses at bank scale.

Design review checklist

Questions that carried from model to layout.

Is each modeled nonideality physical, calibrated, and separable from numerical quantization?
Does the compensation structure scale with rows and columns more slowly than a full $\alpha$ matrix?
Do fixed-point widths preserve convergence across the expected range and multiple seeds?
Are saturation, rounding, reset, and update ordering defined at bit accuracy?

Can the sensor resolve the post-parasitic current step across PVT and mismatch?
Are physical 1T1R cells and logical differential 2T2R weights distinguished in verification?
Can every internal training and inference mode be reached through the test interface?
Does the measurement plan estimate noise and distortion over comparable code populations?