Parallel-bar model ↔ measured prototype → complete SEC account

Connect the accuracy model to the SEC-enabled silicon system.

JxCDC 2024 develops the behavioral/SNDR model for resistive parallel-bar IMC and validates it against the measured 22 nm MRAM prototype. ESSCIRC 2023 presents OCCS and SEC in silicon. JSSC 2025 then unifies the model, correction architecture, fixed-point implementation, measurement protocol, and application result.

Parallel-bar modelDevice variation, BL/SL parasitics, sensor mismatch, and ADC noise determine the available compute SNDR.

Measured macroOCCS and learned SEC factors recover signal quality inside a 22 nm MRAM IMC macro in silicon.

Complete accountJSSC 2025 connects structured attenuation to correction with $\alpha$ , $\gamma$ , and $\theta$ , then to fixed-point hardware, compute SNDR, and measured outcomes.

Research relationship

Three publications expose one model-to-measurement argument.

Model · JxCDC 2024

Model the parallel-bar limit

“Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures” develops the behavioral/SNDR framework and validates it against the 22 nm MRAM prototype.

Open the JxCDC 2024 DOI →

Measured macro · ESSCIRC 2023

Demonstrate correction in silicon

The conference paper presents the 22 nm MRAM macro, OCCS and SEC architecture, measured SNR gain, iso-SNR energy trade-off, and CIFAR-10 final-layer result.

Open the ESSCIRC 2023 DOI →

Synthesis · JSSC 2025

Connect the full chain

The journal extension develops the parasitic model and the $\alpha$ , $\gamma$ , and $\theta$ factorization, then adds OCCS circuit evidence, the fixed-point implementation, the compute-SNDR protocol, and system evaluation.

Open the JSSC 2025 DOI →

Research arcJxCDC 2024 parallel-bar model ↔ ESSCIRC 2023 measured prototype → JSSC 2025 complete SEC account.

Companion and prototype papers

Read the analytical model beside the silicon publications.

JxCDCVol. 10
2024 · pp. 22–30

Parallel-bar analytical companion

Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures

Saion K. Roy and Naresh R. Shanbhag.

The paper develops a behavioral compute-SNDR model for differential resistive parallel-bar IMCs, spanning device variation, BL/SL parasitics, current-mirror mismatch, and ADC noise. It then uses the framework to study dot-product dimension, ADC precision, conductance contrast, device choice, energy, and network accuracy.

Model ↔ silicon

For $N=64$ , a 6-bit ADC, and a 20 mV reference, the model reports $5.17\,\mathrm{dB}$ compute SNDR versus $5.15\,\mathrm{dB}$ from the measured 22 nm MRAM prototype.

Open DOI

S. K. Roy and N. R. Shanbhag, “Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 10, pp. 22–30, 2024, doi: 10.1109/JXCDC.2024.3381888.

ESSCIRC49th IEEE European Solid-State Circuits Conference
2023 · pp. 25–28

Conference paper

Compute SNR-Boosted 22 nm MRAM-Based In-Memory Computing Macro Using Statistical Error Compensation

Saion K. Roy, Han-Mo Ou, Mostafa G. Ahmed, Peter Deaville, Bonan Zhang, Naveen Verma, Pavan K. Hanumolu, and Naresh R. Shanbhag.

The conference account is compact and establishes the result in silicon: the scaling problem, offset-compensating sensing, low-overhead SEC, a measured $2.7\text{–}6\,\mathrm{dB}$ SNR improvement, the one-fifth iso-SNR energy point, and the final fully connected layer CIFAR-10 result.

Silicon

The conference paper’s central result is measured: macro SNR, energy, implementation overhead, and final-layer inference outcomes.

Open DOI

S. K. Roy et al., “Compute SNR-boosted 22 nm MRAM-based in-memory computing macro using statistical error compensation,” in ESSCIRC 2023—IEEE 49th European Solid State Circuits Conference, pp. 25–28, 2023, doi: 10.1109/ESSCIRC59616.2023.10268688.

JSSCVol. 60 · No. 3
March 2025 · pp. 1092–1102
Online 2024

Journal extension

Compute SNDR-Boosted 22-nm MRAM-Based In-Memory Computing Macro Using Statistical Error Compensation

Saion K. Roy, Han-Mo Ou, Mostafa G. Ahmed, Peter Deaville, Bonan Zhang, Naveen Verma, Pavan K. Hanumolu, and Naresh R. Shanbhag.

The journal article is the complete account. It connects the OCCS analysis and Monte Carlo evidence to the parasitic behavioral model, the $\alpha/\gamma/\theta$ formulation, fixed-point convergence, and macro organization, then carries those into per-column MMSE calibration, the code-conditioned SNDR protocol, measured variation, the energy trade-off, and the final-layer ResNet-20 evaluation.

Expanded evidence

Silicon measurements are interpreted alongside circuit simulation, the behavioral model, fixed-point studies, and the SRAM-backed area projection.

Open DOI

S. K. Roy et al., “Compute SNDR-boosted 22-nm MRAM-based in-memory computing macro using statistical error compensation,” IEEE Journal of Solid-State Circuits, vol. 60, no. 3, pp. 1092–1102, Mar. 2025, doi: 10.1109/JSSC.2024.3442013.

Reading key

Four labels separate the layers of evidence.

Silicon

Measured die

ADC-column SNDR, SEC improvement, energy/SNDR points, implemented overhead, and final-layer accuracy.

Circuit simulation

OCCS behavior

Transistor-level mismatch, PVT, Monte Carlo bitline variation, and sensing-area comparison.

Behavioral model

Array and fixed point

Parasitic transfer behavior, $\alpha$ extraction, quantized convergence, and precision selection.

Projection

Storage alternative

SEC area changes from 12.2% as implemented to 3.7% with SRAM-backed storage.

TerminologyThe conference paper reports SNR. The journal uses SNDR to include distortion. SEC means statistical error compensation, and its training learns hardware correction factors.

Canonical records

Open the papers and their publication metadata.

The DOI and IEEE Xplore records provide the paper text, citation metadata, publication history, and related references.

JxCDC 2024 publication record ESSCIRC 2023 on IEEE Xplore JSSC 2025 on IEEE Xplore