Mixed-signal implementation discipline
Turning the model into a testable mixed-signal chip.
Every stage closes against one design identifier: bit-accurate SEC logic, OCCS timing, MRAM interfaces, power delivery, padframe, QFN64 mapping, and test observability. Each stage produces the artifact consumed by the next.
Process map
Four gates carry one design from intent to silicon.
Every gate names its design input, review question, exit artifact, and downstream consumer. An ECO updates the same chain rather than creating a parallel version of the truth.
Intent and model freeze
Input: A definition that still moves cannot be verified. This gate freezes the compute modes, array and ADC organization, OCCS sequence, SEC update and inference semantics, voltage and clock domains, register map, and test access. Four model levels then run shared golden vectors against that frozen definition: ideal, parasitic-aware, circuit, and fixed-point, with rounding, clipping, reset, and update order stated explicitly.
Exit · signed interfaces + golden-vector agreement
Mixed-signal and digital integration
Review: Analog timing and digital control fail at their boundary, not inside either domain. The mixed-signal review covers MRAM access, OCCS auto-zero and evaluate timing, ADC decisions, and startup. The digital review covers CDC/RDC, synthesis equivalence, and timing constraints. Calibration hooks, scan access, and SEC-state controllability are checked last. All of it holds across corners and mismatch.
Exit · correlated block views + constrained testable netlist
Physical and package closure
Implementation: Layout decides whether the modeled signal survives. Design work covers the floorplan, analog quiet regions, power and return paths, reference shielding, and decoupling. The die boundary adds padframe and ESD, the QFN64 bond map, and package parasitics. Signoff then closes DRC/LVS/ERC, antenna, density, timing, EM/IR, and extracted correlation.
Exit · reviewed signoff ledger + package traceability
Release and test readiness
Handoff: The lab inherits whatever this gate writes down. Release identity covers the final database checksum, tool and run identifiers, layer map, and exception dispositions. Bring-up identity covers the package map, register map, board revision, and overlay fingerprint. The bench then needs current limits, smoke vectors, a data schema, and a measurement plan.
Exit · immutable release manifest + executable bring-up plan
Two end-to-end design threads
Track the same decision from model to bench.
A tapeout gate is useful when a choice remains recognizable after it crosses behavioral, RTL, circuit, physical, package, and measurement boundaries.
From convergence study to observable state
- Behavioral sweeps establish one shared factor per physical row.
- Precision studies freeze the 7-bit inference factor and 14-bit update state.
- RTL defines saturation, rounding, reset, update ordering, and shift-based learning rate.
- Scan and control modes expose initialization, training, inference, and stored correction state.
- Bench records bind state to raw codes and the SEC-on measurement configuration.
From sensor mismatch to a raw ADC code
- Circuit analysis defines the auto-zero and evaluate phases.
- Mixed-signal verification aligns OCCS settling, SAR timing, and digital capture.
- Physical closure protects reference, supply, return, and sensitive column paths.
- Pad and QFN64 mapping preserve clock, reset, supply, reference, and raw-code access.
- FPGA sequencing reproduces reset → auto-zero → evaluate → convert → capture.
Cross-domain closure
Four reviews must agree on the same signal path.
The highest-risk decisions sit at interfaces. Four reviews trace the same signal from modeled row current to the raw ADC code recorded at the bench.
Is still representative?
Extracted parasitics, sensor headroom, and input ordering must stay inside the modeled correction range.
Is conversion deterministic?
Auto-zero, evaluation, SAR control, capture, and SEC update phases need unambiguous cycle and reset semantics.
Can the pins carry it?
Pad type, bond map, simultaneous switching, references, supplies, and safe unused states must agree.
Can the result be observed?
The board and FPGA must reach every mode, control timing, limit current, and preserve raw ADC data with metadata.
Review ledger
A signoff record connects every result to the released database.
For every qualified run
- Immutable design identifier and checksum.
- Tool, rule-deck, library, extraction, and corner versions.
- Command/configuration provenance and run timestamp.
- Summary counts linked to reviewable detail.
- Owner and disposition for every nonzero category.
- Cross-probe evidence for representative violations.
- Relationship to the exact handoff database.
For every waiver
- Exact rule, cell/hierarchy, and affected geometry.
- Why the result is intentional rather than ignored.
- Electrical, reliability, yield, and integration impact.
- Foundry or IP-owner concurrence when required.
- Scope narrow enough to prevent masking new errors.
- Revalidation after fill, ECO, or database regeneration.
Release trace
Design checksum → tool and rule-deck versions → reviewed run summaries → exception dispositions → final database digest → handoff receipt.
Design for observability
The bench begins at tapeout.
Post-silicon bring-up becomes an extension of design verification, but only if the design provides the hooks: scan chains, bypasses, raw ADC visibility, independent write/read/MVM modes, controllable clocks, deterministic reset, SEC state access, and current isolation.
Minimum bring-up ladder
Power integrity → static interface → scan-chain loopback → deterministic register access → single-cell read/write → raw ADC capture → MVM → calibration → SEC learning → repeated statistical measurement.
Tapeout outputs
The engineering record follows the chip into the lab.
Each output below resolves a different post-silicon question: what was designed, how it was verified, what was released, and how the packaged part should respond.
Frozen intent
Interfaces, golden vectors, fixed-point rules, corner/mismatch summaries, and post-layout correlation.
Closure ledger
Qualified physical/timing/power runs with their tool context, reviewed exceptions, and database digest.
Die-to-board map
Pad and ESD audit, QFN64 bond map, package orientation, pin domains, and register-level traceability.
Executable bring-up
Board/overlay identity, power sequence, current limits, smoke vectors, expected observables, and data schema.
Design principleThe bench begins at tapeout: every signal that matters after fabrication needs a controllable mode, an observable state, and a documented expected response.