SEC–MRAM IMCModel · architecture · measured silicon GitHub

Overview / Test platform

Python host · PYNQ-Z2 · custom PCB · QFN64

Build a trustworthy path from a script to silicon.

The test platform translates an experiment into scan, read/write, MVM, ADC, and SEC transactions, then carries every raw code and configuration detail back into an analysis record.

Command pathPython declares the experiment. PYNQ sequences typed transactions. The PCB maps them electrically to QFN64.
Silicon actionThe macro executes memory access, OCCS/ADC conversion, MVM, and SEC operations.
Evidence pathRaw codes, status, configuration, and timestamps return to an append-only run record.

System stack

Separate experiment intent from electrical transport.

Each layer owns one transformation. A failure therefore localizes to the experiment protocol, DMA and FPGA transport, board-level electrical mapping, or the chip response.

LAYER 01

Python host

Declares experiment state, seeds, repetitions, metadata, calibration, and analysis.

LAYER 02

PYNQ-Z2

Loads the overlay, transports command/data words, sequences digital timing, and captures results.

LAYER 03

Custom PCB

Maps headers to QFN64, distributes rails and references, decouples, and exposes safe checkpoints.

LAYER 04

MRAM IMC

Executes memory, conversion, MVM, and SEC operations and returns raw observable state.

Evidence returnRun record + analysis ← raw words + status ← FPGA capture ← chip electrical response
Bidirectional stackCommands move from experiment plan to chip timing. Raw ADC codes and metadata move back from the chip to analysis.

One MVM capture

Follow one transaction end to end.

ConfigureDeclare vector and mode

Run ID, chip/board, clock, voltage, SEC state, weight/input vector, and repeat index.

TransportFrame the command

Typed words move through AXI DMA with explicit length, sequence, timeout, and status.

SequenceDrive chip timing

Reset, load, auto-zero, evaluate, SAR conversion, and capture execute in order.

CaptureReturn raw state

ADC code and status return without analysis-side modification.

RecordBind the evidence

Raw result joins configuration digest, overlay hash, timestamp, and fault state.

Annotated measurement setup connecting a Python host, PYNQ-Z2 board, test PCB, and MRAM IMC chip
Measured-silicon setup. Control and capture run from a Python host through a PYNQ-Z2 FPGA to the test board and packaged macro.

PCB design

The board is part of the measurement instrument.

Board parasitics and reference quality enter every measurement, so the TO3 board is built as instrumentation rather than wiring. It carries the QFN64 macro to the PYNQ-Z2, distributes supplies and references, places local decoupling, and exposes checkpoints for power, reset, clocks, and bring-up modes.

Front rendering of the purple custom MRAM IMC test printed circuit board
TO3 test board. The package site, PYNQ headers, power connections, testpoints, and support circuitry form the electrical bridge between FPGA control and the macro.
POWER

Make safe states explicit

Name every rail, return path, current limit, ramp order, decoupling role, and expected unconfigured draw.

SIGNAL

Preserve timing and references

Control clock/scan edges, level compatibility, ground continuity, crosstalk, and analog-reference quietness.

ACCESS

Probe without perturbing

Expose checkpoints for rails, clocks, reset, and critical modes while managing stub and loading effects.

TRACE

Bind revision to silicon

Record board revision, assembly variant, package/lot, modifications, overlay hash, and measurement run together.

Board review

Checks before assembly and before power.

Design-release checklist

  • QFN64 orientation and pin-one convention match the bond map.
  • Every package pin maps to one net, no-connect, or documented reserve.
  • Rail names and nominal/absolute limits agree across chip, schematic, BOM, and scripts.
  • Interface voltage levels and FPGA bank constraints are compatible.
  • Decoupling values and placement are reviewed by rail and load step.
  • Return-current paths remain continuous across connector and plane transitions.
  • Testpoints are labeled and do not compromise sensitive nodes.
  • Fabrication outputs, drill files, stackup, BOM, and assembly drawing share one revision.

Unpowered inspection checklist

  • Visual inspection, package orientation, polarity, solder bridges, and rework log.
  • Resistance-to-ground and rail-to-rail screening against expected ranges.
  • Continuity from FPGA header to key package pins.
  • External supplies set to zero volts with conservative current limits.
  • FPGA I/O held in a defined high-impedance or safe reset state.
  • Oscilloscope/DMM ground strategy reviewed before attaching probes.
  • Board ID, chip ID, operator, time, instruments, and ambient recorded.
  • Stop conditions and shutdown order visible at the bench.
Multiple packaged MRAM IMC test chips, including open-lid packages showing the bonded die
Packaged parts. Open-lid packages make die orientation and wire-bond inspection possible before electrical diagnosis.

Bring-up ladder

Bring-up proceeds from power integrity to statistical measurement.

  1. Apply rails under current limit, then verify voltage and quiescent current.
  2. Assert/reset controls, then confirm no unsafe pin contention.
  3. Validate clock and static GPIO at slow speed.
  4. Shift a known scan pattern and verify loopback/PASS behavior.
  5. Read and write one controlled row, then repeat after reset.
  6. Capture raw ADC codes for deterministic low/high states.
  7. Run a small MVM vector with an analytically known ideal code.
  8. Only then automate calibration, SEC, and statistical sweeps.

PYNQ control plane

Version the overlay as experimental equipment.

A result is only reproducible if the bitstream that produced it can be named. The measured setup uses a PYNQ-Z2 with an XC7Z020 FPGA, a 100 MHz Vivado 2022.2 overlay, AXI DMA, and custom all-pin test logic. The control notebooks sequence scan, read/write, MVM capture, SEC calibration, and network experiments.

DISCOVER

Overlay self-check

Confirm board, bitstream/HWH pairing, clock rate, DMA topology, register signature, and a known loopback before chip access.

TRANSPORT

Typed command framing

Define word width, endianness, opcode, payload length, timeout, and returned status. Reject partial or stale transfers.

PROVENANCE

Hash every binary

Record overlay digest, PYNQ image, Python/package versions, notebook/script commit, pin-map revision, and clock configuration.

TargetPYNQ-Z2 · XC7Z020
ToolVivado 2022.2
Clock100 MHz design
TransportAXI DMA + all-pin logic
Overlay identityEach capture records the bit/HWH checksums, PYNQ image, clock configuration, pin-map revision, and software commit.

Software construction

Turn notebooks into an auditable measurement framework.

The framework separates five concerns: configuration, transport, protocol, acquisition, and analysis. Each notebook operation then becomes a versioned and testable interface.

CONFIG

Describe hardware

Board/chip IDs, endpoints, rail limits, clock, overlay checksum, and instrument resources live in validated configuration.

DRIVER

Move typed data

FPGA, serial, DMA, and instrument drivers expose bounded operations with timeouts and returned status.

PROTOCOL

Declare a run

Scan, read/write, MVM, calibration, and SEC sequences are pure plans with seeds and stop conditions.

ACQUIRE

Keep raw evidence

Append-only records store command, response, timestamp, units, configuration digest, and fault state.

ANALYZE

Derive results

Calibration and SNDR analysis consume versioned raw data and emit provenance, never silently overwriting it.

Runnable analysis module: deterministic sampling → per-column affine calibration → probability-weighted code error → compute SNDR. Open the artifact map →